The present invention relates to the field of electronic circuits, and, more particularly, to latch circuits resistant to single event upset (SEU) such as caused by energetic heavy ions.
Natural or man-made radiation on earth and cosmic rays in space may cause errors in semiconductor devices. When a high energy particle strikes a semiconductor device, it may deposit a charge which can create various effects. For example, where a digital value is stored, as in a memory or a latch, the upset may cause the value stored to change from a one to a zero or vice-versa. A disruption to such a single bit is generally termed a single event upset (SEU). Of course, the upset rate of a semiconductor device can vary based upon the specific structure, size, operating voltage, etc.
Attempts have been made to address the potential disruptions caused by an SEU. For example, U.S. Pat. No. 5,903,717 to Wardrop describes an approach in a fault tolerant computer system using redundant voting at the hardware clock level to detect and correct SEUs. U.S. Pat. No. 5,307,142 to Corbett et al. discloses an asymmetric latch including cross-coupled inverters having a hardened logic state and a soft state. The logic state of the first inverter can only be changed when the voltage on a coupling node is low, and the logic state of the second inverter can only be changed with the coupling node of the inverter is high. One or more such latches can be configured into a memory cell.
U.S. Pat. No. 5,311,070 to Dooley discloses an SEU resistant latch circuit for a gate array standard cell, for example. The latch circuit includes a first latch comprising cross-coupled inverters. Cross-coupled with the first latch is a second latch also having cross-coupled inverters. Respective input nodes of the first and second latches are selectively coupled with the gates of pairs of decoupling transistors so as to bias the gates of the decoupling transistors at predetermined voltage levels. U.S. Pat. No. 6,275,080 B1 to Phan et al. discloses a similar latch circuit with two latches and corresponding isolation transistors.
Along these lines U.S. Pat. No. 6,127,864 to Mavis et al. discloses a temporally redundant latch which redundantly samples data using three sampling circuits which sample the logic data output at three different and distinct sampling times. A sample release circuit selects and outputs a majority of the samples at a fourth time period.
One particularly useful application of an SEU immune or resistant latch circuit is for spaceborne DC-to-DC converter applications. A typical DC-to-DC converter uses one or more latches to control a pulse width modulator. The pulse width modulator, in turn, drives one or more power output devices. The switching rates needed for the pulse width modulator latches may be on the order of several hundred kilohertz. One SEU or a series thereof may cause the converter to suffer a lowered efficiency, or possibly enter an unstable condition resulting in damage or failure.
In view of the foregoing background, it is therefore an object of the present invention to provide an SEU resistant latch circuit and associated methods, such as may be advantageously used in a pulse width modulation converter circuit, for example.
This and other objects, features and advantages in accordance with the present invention are provided by a redundant latch circuit comprising a plurality of latches, a majority voting circuit having inputs connected to the latch outputs, and a feedback reset circuit connected to the latch outputs and driving the latch reset inputs. More particularly, each latch may have a set input for receiving a respective redundant set signal, a reset input for receiving a respective redundant reset signal, and an output indicating a set or reset state of the respective latch. The majority voting circuit may have inputs connected to the outputs of the latches, and an output indicating a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise. In addition, the feedback reset circuit may have inputs connected to the latch outputs, and outputs connected to the reset inputs of the latches. The feedback reset circuit may switch at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state. Accordingly, the redundant latch circuit enjoys resistance to SEUs.
The feedback reset circuit may also have inputs for receiving the redundant reset signals for the latch circuit. The feedback reset circuit may also drive the reset inputs of the individual latches so that the latches switch to the reset state also based upon the redundant reset signals.
The feedback reset circuit may include an EXCLUSIVE OR logic gate having inputs connected to the latch outputs and having an output. A respective reset logic circuit may be connected between the output of the EXCLUSIVE OR logic gate and the reset input of each latch. Each reset logic circuit may include an OR logic gate having inputs connected to the output of the EXCLUSIVE OR gate and receiving a respective redundant reset signal. Each reset logic circuit may also include an INVERTER logic gate having an input receiving a respective redundant set signal, and an AND logic gate having inputs connected to the outputs of the OR logic gate and the INVERTER logic gate. The output of the AND logic gate may be connected to the reset input of a respective latch.
The majority vote circuit may be provided by at least one AND logic gate. The plurality of redundant latches may be as few as two in number.
The redundant latch circuit is especially advantageously used in a power converter, such as a DC-to-DC power converter, for spaceborne applications, for example. The converter may include at least one power switch, and a pulse width modulator. The pulse width modulator may include a drive circuit generating redundant set and reset signals, and a redundant latch circuit as described above connected between the drive circuit and the power switch.
Another aspect of the invention relates to a method for providing resistance to SEUs in a redundant latch circuit of a type comprising a plurality of latches. Each latch may have a set input for receiving a respective redundant set signal, a reset input for receiving a respective redundant reset signal, and an output indicating a set or reset state of a respective latch. The method preferably comprises performing majority voting on the outputs of the latches, and receiving as feedback signals the outputs of the latches to drive the reset inputs of the latches for switching at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state to thereby provide resistance to SEUs. The majority voting may generate an output indicating a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise.